# Linux 7.4 and RISC-V: faster user copies on distro kernels, crash hotplug and the B extension - **Published on:** 2026-10-31 - **Category:** News - **Original page:** https://free-linux.com/articles/linux-7-4-risc-v Linus Torvalds merged the RISC-V changes for Linux 7.4 on 29 October 2026. The user-copy optimisation for cores with fast misaligned accesses is now decided at boot, so it reaches generic kernels; there's also crash hotplug, support for the B and Zic64b extensions and a hardened shadow stack. --- The **Linux 7.4** merge window opened after Linux 7.3 came out on 18 October, and on **29 October 2026** Linus Torvalds merged the **RISC-V** pull sent by **Paul Walmsley**, one of the architecture's maintainers. It's 28 commits with no big headline, but several of them will reach anyone running a distribution kernel on RISC-V hardware. ## Faster user copies, now on generic kernels too The most practical change comes from **Andy Chiu**. When the kernel copies data between its own memory and a program's (a *user copy*), it runs code that aligns accesses in software for processors that handle misaligned accesses badly. On cores that handle them well, skipping that code **raises copy bandwidth by up to 11.4%**, according to the figure in the patch. That optimisation already existed, but only at build time: it depended on `HAVE_EFFICIENT_UNALIGNED_ACCESS`, which in turn requires marking the kernel as non-portable. No distribution does that, because its kernel has to boot on very different boards. In Linux 7.4 the decision moves to **boot time**: the kernel measures how fast misaligned accesses are and, if the CPU is quick, turns the jump into the alignment code into a no-op through a *static key*. So the same generic Debian, Fedora or Ubuntu kernel gets the speed-up wherever the hardware allows it. ## Crash hotplug and other kernel plumbing - **Crash hotplug** (Rui Qi): when CPUs or memory are added or removed on a running system, the header that describes the machine to the crash-capture kernel (`elfcorehdr`) is kept up to date. Without it, a crash after a topology change produced a `vmcore` that didn't match the real machine. The implementation follows the x86 model. - **Page tables** (Jisheng Zhang): `pgtable_l4_enabled()` and `pgtable_l5_enabled()`, which say whether 4 or 5 paging levels are in use, return a value that never changes after boot. They are now patched in during early boot, or fixed in Kconfig for purpose-built kernels, with the new `RISCV_ISA_SV48` and `RISCV_ISA_SV57` options. - **Context switch**: an unnecessary read of the `sstatus` register is avoided, and the vector unit's context switch is reorganised ahead of future optimisations. There's also a new `kselftest` for vectorised user copy. - **PCIe**: bus reassignment now depends on the `PCI_REASSIGN_ALL_BUS` flag, as on ARM64. - `RISCV_ALTERNATIVE` is no longer optional, now that XIP kernel support has been removed. ## New extensions visible to user space **Andrew Jones** adds the **"B" extension** to `hwcap` and `hwprobe`, the interface programs use to ask what the CPU can do. "B" bundles the bit-manipulation extensions Zba, Zbb and Zbs, and the kernel makes sure that when it reports B, all three are set as well. Programs can now query it directly, as they already could with F, D, C or V. **Zic64b**, which says cache blocks are 64 bytes, can now be declared and reported too. It has been added to the device trees of the **SpacemiT K1 and K3** and the **Sophgo SG2044** SoCs. Device tree validation also now requires the block size of cache-management operations to be specified (the Zicbom, Zicbop and Zicboz extensions). ## Security and errata **Samuel Holland** hardens the *shadow stack*, the protected stack that defends against attacks rewriting return addresses: the restore token's address is now bounds-checked before use so it can't become an attack vector. Another fix makes the shadow stack and indirect-branch landing pad control functions write the `envcfg` register only when they act on the current task. On MIPS-designed RISC-V hardware, errata can now be applied during early boot, and on the **P8700** the kernel stops using the `WFI` instruction, which is buggy on that chip, and uses `mips.pause` instead. ## KVM The RISC-V virtualisation changes for 7.4 arrive through the KVM tree: support for the `KVM_PRE_FAULT_MEMORY` ioctl, a fix for inter-processor interrupt delivery when `vcpu_id` values are out of order, and the option to expose the Zicclsm, Ziccamoa, Ziccif and Za64rs extensions to guests. ## When it lands If the usual two-week merge window holds, the first release candidate, Linux 7.4-rc1, will be out this **Sunday, 1 November**, with the final release around late December or early January. Kernel versions and dates are on the [Linux page](/linux-kernel). To see how a distribution makes use of specific architecture extensions, have a look at [using custom RISC-V instructions on Ubuntu](/articles/ubuntu-risc-v-instrucciones-personalizadas). And for comparison with an earlier cycle, here's what [Linux 7.1](/articles/linux-kernel-7-1) brought. **Sources:** [merge "riscv-for-linus-7.4-mw1"](https://git.kernel.org/torvalds/c/1b8b67503725fa6deb3a4f00ea61f982bd00c152) and [merge "kvm-riscv-7.4-1"](https://git.kernel.org/torvalds/c/7e60162b16f9da0d2fa83da5c1723b6853a0ac1d) in Linus Torvalds' tree; commits by Andy Chiu ("riscv: optmize ucopy for has_fast_unaligned_accesses"), Rui Qi ("riscv: crash: Add crash hotplug support") and Andrew Jones ("riscv: Add B to hwcap and hwprobe").